FIG. 1 illustrates a schematic diagram of a typical current steering digital-to-analog converter (DAC) 100. The current steering DAC 100 consists of a plurality of segments 110-1 to 110-n for selectively steering current to either the positive output OUTP or the negative output OUTN. Each of the current steering segments, as represented by segment 110n, consists of a current-setting field effect transistor (FET) M1n, a cascode FET M2n, and a pair of differential FETs M3n and M4n. 
The current steering DAC 100 may further consists of a thermometer code decoder 120 including a switch driver 122 which receives the binary coded digital input signal that is to be converted into a differential analog signal at the outputs OUTP and OUTN of the current steering DAC 100 and generates the appropriate driving signals D1 to Dn and DB1 to DBn, in response to a conversion clock signal, for respectively controlling the current steering of the current steering segments 110-1 to 110-n. For instance, as the value of the input digital signal increases, the thermometer code decoder 120 generates binary signals D1 to Dn and DB1 to DBn to cause more current steering segments 110-1 to 110n to steer current to the positive output of the DAC 100. Conversely, as the value of the input digital signal decreases, the thermometer code decoder 120 generates binary signals D1 to Dn and DB1 to DBn to cause less current steering segments 110-1 to 110n to steer current to the positive output of the DAC 100.
More specifically, the source of each of the current-setting FETs M1n is connected to a power supply terminal AVDD, the gate of each of the current-setting FETs M1n receives a control voltage VGATE, and the drain of each of the current-setting FETs M1n is connected to the source of the corresponding cascode FET M2n. The gate of each of the cascode FETs M2n receives a control voltage VCASC, and the drain of each of the cascode FETs M2n is connected to the corresponding sources of the differential FET pair M3n and M4n. The gates of each of the differential FET pair M3n and M4n respectively receive the corresponding control signals Dn and DBn generated by the thermometer code decoder 120. The drains of each of the differential FET pair M3n and M4n are coupled respectively to the positive output OUTP and negative output OUTN of the current steering DAC 100.
The control voltage VGATE sets the current through each of the current steering segments 110-1 to 110-n. The control voltage VCASC sets the drain-to-source voltage of the current-setting FETs M1 to M1n in a manner that the output impedances of the current steering segments 110-1 to 110-n are relatively high. The control signals Dn and DBn causes the corresponding differential FET pairs M3n and M4n to steer the current to either the positive output OUTP or the negative output OUTN. For example, if the control signal Dn is a logic high and DBn is a logic low, differential FET M3n is turned “off” and differential FET M4n is turned “on”. Accordingly, the current in the corresponding current steering segment 110n is steered to the negative output OUTN of the DAC 100. Conversely, if the control signal Dn is a logic low and DBn is a logic high, differential FET M3n is turned “on” and differential FET M4n is turned “off”. Accordingly, the current in the corresponding current steering segment 110n is steered to the positive output OUTP of the DAC 100.
A drawback of the current steering DAC 100 stems from the fact that as a current steering segment 110n changes the current steering between the positive and negative outputs OUTP and OUTN (which are typically at different voltage levels), the voltage at the summing node Sn (at the sources of the differential FET pair M3n and M4n) shifts due to the finite intrinsic gain of the differential FET pair M3n and M4n. The shifting of the voltage at the summing node Sn is proportional to the voltage difference between the voltages on the positive and negative outputs OUTP and OUTN of the DAC 100. When this voltage shifts, the capacitance at the summing node Sn has to be recharged. The charge flowing to the capacitance affects the converter output signal, and creates harmonic distortion. This distortion is more prevalent at higher output tone frequency. Thus, the dynamic range of the DAC 100, typically referred to in the art as the Spurious Free Dynamic Range (SFDR), is limited by the shifting voltage at the summing node Sn.
Accordingly, there is a need for an apparatus and method which reduces the variation of the voltage at each of the summing nodes to improve the dynamic range and output signal quality of the DAC. Such need and other are addressed in the detailed description of the invention as follows.